`include "../../src/Mux.v"
`timescale 1ps/1ps

module test;

reg[31:0] data0, data1;
reg ctrl;

wire[31:0] outData;

initial 
begin
    data0 = 32'd10;
    data1 = 32'd20;

    #10 ctrl = 0;

    #10 ctrl = 1;

    #10 $stop;

end

Mux U0(data0, data1, ctrl, outData);

initial
begin
    $dumpfile("test.lxt");
    $dumpvars;
end

endmodule